IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Applications Information
Operation with 12V Adapter
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:
1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5982A/MAX5982B/MAX5982C.
2) Use large SMT component pads for power dissipat-
ing devices such as the MAX5982A/MAX5982B/
MAX5982C and the external diodes.
3) Use short and wide traces for high-power paths.
4) Place enough vias in the pad for the EP of the
MAX5982A/MAX5982B/MAX5982C so that heat gen-
erated inside can be effectively dissipated by the
PCB copper. The recommended spacing for the vias
is 1mm to 1.2mm pitch. The thermal vias should be
plated (1oz copper) and have a small barrel diameter
(0.3mm to 0.33mm).
2-EVENT
CLASSIFICATION
(ASSERTED ON)
GND
RJ-45
AND
BRIDGE
RECTIFIER
R DET
24.9k I
V DD
2EC/WAD
2EC
PG
IN+
ENABLE
GND
SMAJ58A
68nF
DET
CLS
MAX5982A
MAX5982B
MAX5982C
I.5mA
WAD
12V
DC-DC
CONVERTER
R CLS
BATTERY
-54V
V SS
RTN
IN-
THIS CIRCUIT ACHIEVES
PROPER 2EC LOGIC WHEN
BATTERY IS < 12.5V
WALK MODE
INPUT
WK
MAX5982A/MAX5982B ONLY
SL
1k I
60.4k I
ISOLATED SLEEP
MODE INPUT
ULP
-54V
LED
ULTRA-LOW-POWER
SLEEP
-54V
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
-54V
14
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